The present invention relates to a solid state image pickup apparatus. More particularly, this invention relates to a solid state image pickup apparatus with a MOS type of image pickup device.
An image pickup tube or a solid state image pickup device has been used as a device for converting an optical image to an electric signal. The solid state image pickup device includes a CCD type of image pickup device with charge-coupled devices (CCD) and a MOS type of image pickup device with MOS transistors. The MOS type of image pickup device has an advantage that the cost of fabrication is lower than that of the CCD type of image pickup device because the MOS type of image pickup device can be fabricated using an ordinary fabrication process used for manufacturing a CMOS transistor.
The MOS type of image pickup device has another advantage that consumed current is about one tenth of the CCD type of image pickup device. Further, the solid state image pickup apparatus with a MOS type of image pickup device has an advantage that the solid state image pickup apparatus can be formed on a single chip if a circuit other than pixels (such as a circuit for reading pixel signals) is formed by MOS transistors because the pixels and the circuit other than the pixels can be fabricated on the same semiconductor substrate.
FIG. 1 is a schematic circuit diagram showing a configuration of a portion of the conventional type of solid state image pickup apparatus with a MOS type of image pickup device.
This solid state image pickup apparatus comprises pixels formed with sensors S00 to Smn and switching transistors Mr00 to Mrmn which are arranged in a matrix. Further, there are provided vertical selection lines V0 to Vm. Each of the vertical selection lines V0 to Vm is commonly connected to a group of pixels that belong to the same row. Further, there are provided horizontal selection lines H0 to Hn. Each of the horizontal selection lines H0 to Hn is commonly connected to a group of pixels that belong to the same column. Further, there are provided sample holding circuits SH0 to SHn to which the horizontal selection lines H0 to Hn are respectively connected.
The solid state image pickup apparatus further comprises a vertical scanning circuit 11 which sequentially selects the vertical selection lines V0 to Vm. Switching elements Mc0 to Mcn are provided for selecting the sample holding circuits SH0 to SHn. A horizontal scanning circuit 12 is provided which sequentially turns ON the switching elements Mc0 to Mcn. A read bus 13 which is a signal line common to the sample holding circuits SH0 to SHn is provided. An output amplifier 14 is connected to this read bus 13. In FIG. 1, reference numeral 15 represents an output terminal.
FIG. 2 is a circuit diagram that shows the circuit near the read bus in more detail. The sample holding circuits SH0 to SHn have driving transistors M0 to Mn. Each of the driving transistors M0 to Mn outputs a pixel signal read from the corresponding pixel.
The gate of each of the driving transistors M0 to Mn is supplied with a pixel signal and the drain is grounded. Thus, the transistors are used as a source followers. The switching elements Mc0 to Mcn consist of switching transistors. A selection signal is input from the horizontal scanning circuit 12 to the gates of each of there switching transistors.
Operation of the solid state image pickup apparatus shown in FIG. 1 and FIG. 2 is explained below. Each of the sensors S00 to Smn converts the incident light into an electric signal. The vertical scanning circuit 11 sequentially outputs the selection signals to the vertical selection lines V0 to Vm.
Accordingly, the switching transistors Mr00 to Mrmn are turned ON row by row. The signals detected by sensors S00 to Smn are stored in the sample holding circuits SH0 to SHn. The switching elements Mc0 to Mcn are then successively turned ON based on the selection signals output from the horizontal scanning circuit 12. These signals, namely the pixel signals stored in the sample holding circuits SH0 to SHn, are sequentially output to the read bus 13. The pixel signals output to the read bus 13 are amplified by the output amplifier 14 and are output from the output terminal 15.
In the conventional type of solid state image pickup apparatus, however, the same number of switching elements Mc0 to Mcn as that of the sample holding circuits SH0 to SHn are connected to the read bus 13. Accordingly, the capacitance of the read bus 13 becomes large due to the parasitic capacitance such as junction capacitance of transistors forming the switching elements Mc0 to Mcn. Therefore, there comes up a problem that it is difficult to increase the amount of pixel signals in order to provide a large number of pixels or to more speedily output pixel signals in order to increase the frame rate.
In order to read the pixel signals more speedily, a bias current of the read bus 13 may be increased by upsizing the driving transistors M0 to Mn for the sample holding circuits SH0 to SHn to enhance the driving capability of the current.
In order to increase the amount of current, however, the size of the transistors forming the switching elements Mc0 to Mcn has to be increased. This increases the parasitic capacitance, and as a result the capacitance of the read bus 13 increases further. Therefore, even if bias current to the read bus 13 is increased, it is difficult to achieve a sufficiently high speed.
It is an object of the present invention to provide a MOS type solid state image pickup apparatus which can read out the pixel signals at high speed.
The solid state image pickup apparatus according to one aspect of the present invention comprises, for instance, four read buses which read-out the pixel signals from a plurality of pixels, and one integrated bus which can be connected to the four split buses. The split buses are connected to the integrated bus through a switching element.
According to the above invention, since the read bus is split into a plurality of split buses, the number of switching elements to be connected to one split bus is reduced. Accordingly, the capacitance of the split bus is reduced and hence the pixel signals can be read at a higher speed.
Further, a constant-current source for the integrated bus provides a bias current to the integrated bus and a constant-current sources for the split buses provide a bias current to each of the split busses. However, the constant-current source for the integrated bus provides the bias current to the integrated bus which is greater in magnitude than the bias current provided to the split busses by the constant-current sources for the split buses. Accordingly, the degree of variations in the bias current passing through the read bus is decreased. Therefore, variations in the read signals due to different buses through which the signals pass can be suppressed to the level as low as possible.
Further, a bias-potential application circuit for the split buses maintains a potential of each of the split buses to substantially the same level regardless of the selection status of the split bus. Similarly, a bias-potential application circuit for the integrated bus maintains a potential of the integrated bus to substantially the same level as that of the split buses. Therefore, noise occurring when a switching element selects a split bus can be decreased.